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MD3880 4-Channel Low-Noise Amplifier
Features
2.5V 0.125V operation 4 independent channels Fully differential inputs and outputs 0.74nV/Hz input-referred noise at 18.5dB gain Ultra low current noise 0.35pA /Hz 600k /17.5pF internal input impedance 100MHz amplifier bandwidth Linear-in-dB continuous variable gain control Four digital programmable gain settings for PGA 60MHz whole channel bandwidth at maximum gain 70dB maximum channel gain Variable gain scaling control Active input impedance matching
General Description
The MD3880 is a 4-channel, variable gain amplifier (VGA) paired with a low noise amplifier (LNA) that delivers fully differential input and output for ultrasound applications. The 18.5dB gain of the LNA allows the whole channel to have 0.74nV/Hz of input-referred voltage noise at 5MHz. The LNA is capable of active impedance control to improve noise performance, provided that the applications can take advantage of input impedance matching. The output of the LNA is fed directly into the VGA without using an external coupling capacitor. The VGA is composed of a voltage controlled attenuator (VCA) and a programmable gain amplifier (PGA). The VCA can be continuously varied linear-in-dB by a control voltage (VTGC) from 0dB to a maximum 47dB. In addition, the gain of the PGA can be varied between four discrete settings.
Applications
Medical ultrasound receiver LNA & TGC Doppler signal amplification Transducer signal conditioning
Typical Application Circuit
+2.5V C5 VDD EBC PDC PA1 P IN1 P IN1 N PA1 N PA2 P IN2 P IN2 N PA2 N PA3 P IN3 P IN3 N PA3 N PA4 P IN4 P IN4 N PA4 N
LNA LNA LNA LNA
INT. REF.
VCA
PGA
OUT1 P OUT1 N
VCA
PGA
OUT2 P OUT2 N
VCA
PGA
OUT3 P OUT3 N
VCA
PGA
OUT4 P OUT4 N
GND
GSC TGC PG1 PG0
MD3880
Ordering Information
Package Option Device 84-Lead BCC+ 7x7mm body, 0.80mm height (max.), 0.50mm pitch MD3880B2-G
Pin Configuration
Pin A1 Mark A44 B40 B32 A35
A1 B1
A34 B31
MD3880
-G indicates package is RoHS compliant (`Green')
B11 A12
B21 A23 B12 (Top View) B20
Absolute Maximum Ratings
Parameter VDD, positive supply VIN, any input pin voltage range Operating temperature Storage temperature Power dissipation Value -0.5V to +3.5V -0.5V to VDD -40C to +85C -65C to +150C 2.0W
A13
84-Lead BCC+
A22
Product Marking
YYWW MD3880B2 LLLLLLLLL
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
L = Lot Number YY = Year Sealed WW = Week Sealed = "Green" Packaging
84-Lead BCC+ Package
Operating Supply Voltages
(Over operating conditions unless otherwise specified, VDD = +2.5V, TA = 25C)
Sym VDD IDDQ IDD PWR PSRR
Parameter Power supply VDD supply current VDD supply current Power dissipation PSRR
Min 2.375 -
Typ 2.5 75 700 175 -60
Max 2.625 45 -
Units V mA mA mW mW dB
Conditions TA = -40C to +85C Power down, PDC=1, total of all channels PDC = 0 Total of all channels Per channel f = 100kHz
Logic Data and Clock Inputs Characteristics
(Over operating conditions unless otherwise specified, VDD = +2.5V, TA = 25C)
Sym VIH VIL IIH IIL CIN
Parameter Input logic high voltage Input logic low voltage Input logic high current Input logic low current Input logic pin capacitance
Min 0.8VDD 0 -1.0 -
Typ 10
Max VDD 0.2VDD 1.0 -
Units V V A A pF
Conditions -----------
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MD3880
Electrical Characteristics
(All typical values are under the condition of TA= + 25C, VDD = 2.5V, Load resistance = 1k across the differential outputs, CLOAD = 1pF, fIN = 10MHz, PG0 = 0, PG1 = 0, VGSC = 2.5V, VCM = 1.25V, GAINLNA = 18.5dB, Single-ended input: RS = RIN = 50. RIN is formed by active termination with RFB = 237 and CFB, Differential signal output, unless otherwise noted.)
Low Noise Amplifier
Sym GLNA RIN CIN IBIAS CMRR VIN VIN-NOISE IIN-NOISE NF BW Parameter Amplifier gain Input resistance Input capacitance Input bias current Common mode rejection ratio Input voltage range Input voltage noise, 5MHz Input current noise Noise figure Bandwidth Min Typ 18.5 600 17.5 1 -65 210 0.74 0.35 2.3 3.7 100 Max Units dB k pF nA dB mV nV/Hz pA/Hz dB dB MHz Conditions --Without active termination Without active termination From ESD leakage PG0 = PG1 = VDD, VTGC = 2.0V, f = 1MHz AC-coupled Without active termination Without active termination f = 5MHz, without active termination RS = RIN = 50, f = 5MHz with active termination Small signal bandwidth
Overall Channel
Sym Gain BWVGA SRVGA VOVGA ROUT IOUTS VIN-NOISE IMD Parameter Whole channel gain -3dB bandwidth Slew rate Output signal range Output Impedance Output short-circuit current Input voltage noise Intermodulation distortion, two-tone Min HD3 Third harmonic distortion HD2 Second harmonic distortion AOUT1dB 1dB compression point Typ 70 60 500 4 3 40 0.8 -76 -70 -73 -69 -55 -47 -87 -70 -53 -51 -1.3 Max dBm dBc dBc Units dB MHz V/s VPP mA nV/Hz dBc Conditions Without active termination, max. gain Small signal bandwidth at max. gain --RL > 1k differentially f = 5MHz, single ended --At max. gain and 5MHz 1MHz , VOUT = 1VPP, 30dB gain 10MHz , VOUT = 1VPP, 30dB gain VOUT = 1VPP, 1MHz, 30dB gain VOUT = 1VPP, 10MHz, 30dB gain VOUT = 1VPP, 1MHz, 10dB gain VOUT = 1VPP, 10MHz, 10dB gain VOUT = 1VPP, 1MHz, 30dB gain VOUT = 1VPP, 10MHz, 30dB gain VOUT = 1VPP, 1MHz, 10dB gain VOUT = 1VPP, 10MHz, 10dB gain VOUT = 1VPP, f= 10MHz, 8dB gain
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MD3880
Overall Channel
Sym CSTK tgd tOLR VDC-OUT Parameter Crosstalk Group delay variation Overload recovery time DC output level, VIN = 0 Min Typ -78 2 5 1.25 Max Units dB ns ns V Conditions PG0 and PG1 = 1, 30dB gain, 1MHz, 1VPP at adjacent channel 2 MHz < f < 50 MHz, Full Gain Range 8dB Gain, VIN = 50mVPP to 1VPP change, f = 10MHz ---
Note: VIN is the voltage at the non-inverting node of the amplifier.
Accuracy
Sym GSLOPE GMAT EGAIN VOS-OUT Parameter Gain slope Ch. to ch. gain matching Gain error Output offset voltage Min 31 Typ 33 0.1 0.8 20 Max 35 Units dB/V dB dB mV Conditions VGSC = 2.5V VTGC = 0V or 2.0V Referenced to best fit dB-linear curve, 0.5V < VTGC < 1.7V Reference to 1.25V
Gain Control Interface
Sym VTGC VGSC RGSC RTGC tdTGC Parameter Gain control voltage Gain slope voltage Input resistance of GSC Input resistance of TGC Response time Min 0 2.0 Typ 120 1.5 0.2 Max 2 2.5 Units V V k M s Conditions Linear in dB, See gain scaling diagram About 41dB/V at 2.0V and 33dB/V at 2.5V --Connected to 3/4 VGSC 95% full gain change
PGA Gain Control Table
PG1, PG0 0,0 0,1 1,0 1,1 PGA Gain (dB) 35 40.5 46 51.5
TGC and GSC Voltage for Gain Scaling
0 Max. Slope
Configurations for Active Feedback
RFB CFB CC
VCA Attenuation (dB)
Min. Slope
PA RS
- 47 0 TGC Voltage (V) 1.7
LNA
4
MD3880
Pin Configuration
Pin # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 Pin Name IN1P IN1N PA1P PA2N AVDD PA2P PA3N AVDD PA3P AGND IN4P IN4N AGND AGND EBC AGND GSC CM0 A0 PG1 GND Pin # A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 Pin Name AGND AVDD AVDD AGND OUT3P CM3 OUT3N OUT2P CM2 OUT2N OUT1P AVDD AVDD AGND GND VDD VDD GND GND VDD VDD Pin # A43 A44 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 Pin Name GND AGND PA1N AVDD AGND IN2P IN2N AGND IN3P IN3N PA4N AVDD PA4P NC GND PDC AVDD NC A1 PG0 TGC Pin # B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 Pin Name NC OUT4P CM4 OUT4N AVDD AVDD AGND AVDD AVDD AGND CM1 OUT1N NC NC NC NC NC NC NC NC NC
Pin Description
Pin Name VDD GND AVDD AGND IN1~4P IN1~4N PA1~4P PA1~4N OUT1~4P OUT1~4N PDC EBC GSC A0, A1 PG0, PG1 TGC CM0~4 Description VDD voltage supply Ground Analog supply Analog ground Positive polarity LNA input of channel 1~4 Negative polarity LNA input of channel 1~4 Channel 1~4 LNA positive output Channel 1~4 LNA negative output Positive polarity PGA output of channel 1~4 Negative polarity PGA output of channel 1~4 PDC = 1, power down and enable external biasing, 450k intermal pull down External current biasing Input of gain scaling control for all channels Reserved, should connect to AVDD PGA Gain select inputs (PG0 = LSB, PG1 = MSB) Attenuator control input 0.1F bypass capacitors to ground
5
MD3880
84-Lead BCC+ Package Outline (B2)
7x7mm body, 0.80mm height (max.), 0.50mm pitch
D B40 A44 Pin A1 Mark A1 Note 1 (Index Area E/2 x D/2) 11 x eT E 10 x eT E2 B1 D2
Detail A
Detail A 8 x eT 9 x eT
Top View
Bottom View
b L eR A2 A A1 Seating Plane L L1 eT/2 eT Terminal Tip
Side View
Detail A
Notes: 1. Details of Pin 1 identifier are optional, but must be located within the indicated area. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol MIN Dimension (mm) NOM MAX
Drawings not to scale.
A 0.65 0.80
A1 0.05 0.10
A2 0.60 0.65 0.70
b 0.20 0.30 0.40
D 6.85 7.00 7.15
D2 4.55 4.70 4.85
E 6.85 7.00 7.15
E2 4.55 4.70 4.85
eR 0.50 BSC
eT 0.50 BSC
L 0.20 0.30 0.40
L1 0.10 REF
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-MD3880 NR051407
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